One of the most demanding applications of high-speed data communications is by an on-chip serializer/deserializer (SERDES) used for serial data communication between integrated circuits (chips) on, for example, a circuit board. Typically, a SERDES on one chip communicates with a SERDES on another chip using one or more high-speed serial input/output (HSIO) channels to communicate at data rates in the multi-Gb/s range. Because the chips communicating via HSIO channels are usually individually “packaged” (e.g., in a plastic or ceramic encapsulate having conductors therein used to couple signals and power between the chip and external circuitry) and the packaged chips are in turn attached to a circuit board via solder balls or other means, broadband signal integrity at multi-Gb/s speeds may be compromised due to imperfections and impedance mismatches within the package.
One measure used to evaluate broadband signal performance for an HSIO channel within a package is the signal return loss (the ratio of incident signal power to reflected signal power as measured at the solder balls on the package, the reflected signal coming from discontinuities in the internal signal conductors within the package and from impedance mismatches), measured where the package couples to the circuit board (e.g., at the solder balls). The higher the return loss, the poorer the quality (e.g., a smaller eye opening) of the broadband digital signals passing through the package. Excessive signal return loss in at least some existing chip package designs indicates poor HSIO channel performance for those packages. Thus, there is a desire for one or more chip package designs that provides satisfactory HSIO channel performance at multi-gigabit data rates.